1. Field of the Invention
The invention relates to the field of forming self-aligned source and drain regions for field-effect transistors.
2. Prior Art
Typically during the formation of a field-effect transistor, ion implantation is used to align a source and drain region with a gate (and/or with gate spacers in some processes). The ion implantation damages the crystalline structure of the silicon substrate necessitating thermal annealing. During the annealing the implanted dopant diffuses thereby deepening the source and drain regions. These deeper regions make it difficult to control the adverse effects of short channels. Ideally, to control the short channel effects where effective channel lengths are in the order of 0.1 um or less, the source and drain regions should be extremely shallow and heavily doped (e.g., 0.05 to 0.1 um versus 0.2 to 0.4 um for ion implanted regions).
Scaling implanted p+ junctions is particularly difficult since the light boron (B.sup.11) ions channel during implantation and secondly, since the ions damage the silicon bonds causing point defects. These point defects significantly increase the diffusion of the boron atoms (up to 1000 times) during subsequent thermal annealing. Thus, even for light ions, such as B11, and low energy implants, the implant damage results in enhanced diffusion.
One solution to this problem is to make amorphous the silicon substrate before the B11 implant since this reduces channeling. However, the net result is not a significantly shallow profile since the damage to the silicon lattice leads to enhance diffusion of the implanted B11.
Another technique for solving this problem is to diffuse the portion of the source and drain regions adjacent to the gate (tip or tip region) from doped spacers and to form the more heavily doped main portions of the source and drain regions by ion implantation. This provides some advantage over the ion implantation of both the tip region and main portion of the source and drain regions but implant damage from the source/drain implant still affects the depth of the diffused tip region resulting in degraded short channel effects. Short channel effects are discussed in numerous publications such as Silicon Processing for the VLSI Era, Vol. 2, by S. Wolf, published by Lattice press, see Section 5.5, beginning at page 338.
As will be seen, the present invention permits the simultaneous doping of an ultra shallow lightly doped source and drain tip regions, main portions of the source and drain regions and doping of the polysilicon gate without ion implantation.